Methods for forming alignment marks on semiconductor devices

ABSTRACT

A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.10/960,660, filed Oct. 7, 2004, and claims priority under 35 U.S.C. §119to Korean Patent Application No. 10-2003-0070974, filed on Oct. 13,2003, in the Korean Intellectual Property Office, the disclosures ofwhich are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to analysis of semiconductor devices, andmore particularly, to semiconductor devices having alignment marks andrelated methods.

BACKGROUND OF THE INVENTION

Semiconductor memory devices generally include arrays of cells that formmemory units. Each of the cells can include a transistor pattern havinga gate and source/drain regions. To obtain ever higher integrationdensity in the memory devices, gate lengths and intervals between gatesare continuing to be reduced. For example, in some memory devices thesource/drain regions can have a width of less than several tens ofnanometers.

The small size of some transistor patterns may cause them to bedifficult to observe with an optical microscope. Consequently, it can bedifficult to detect and identify a particular failed cell in a memorydevice. For example, it may not be feasible to optically count numeroussmall cells in a memory device in an attempt to determine an address ofa failed cell. Moreover, when a cell region has failed because of adoping abnormality, such a failure may be difficult to optically observebecause the region may appear optically identical to other normalregions.

One approach to analyzing memory cells or other device features is toexpose a vertical profile of a cell that is to be analyzed. For example,it can be desirable to obtain a vertical profile of a failed celladdress in a memory device by grinding a side face of the memory deviceto expose regions of the failed cell address. However, it may not befeasibly to optically identify a failed cell address with the memorydevice, and then to expose regions of that particular cell address sothat they may be further analyzed.

A cell region can be inspected with a scanning microscope (SCM). A SCMcan include a capacitance sensor and a probe. The capacitance sensor iselectrically connected to the probe for measuring a capacitance betweenthe probe and the cell region. The probe and cell region may, forexample, have nanometer feature sizes. The capacitance sensor includes ahigh-frequency oscillator and an electrical resonator. The capacitance,which can have a very low value, is measured by varying a resonancefrequency that is based on the capacitance. For example, a highfrequency measured signal can be modulated onto a low frequency signal.A differential value of the capacitance relative to a voltage may bemeasured using a lock-in amplifier. The SCM can measure carrierconcentrations and second dimensional doping profiles of the cellregions.

Accordingly, if a failed cell region can be exposed for analysis by aSCM, the doping profiles measured by the SCM may provide an answer as towhy the cell region failed.

SUMMARY OF THE INVENTION

According to some embodiments of the present invention, a semiconductordevice includes alignment marks that are aligned with device features.The semiconductor device includes a device feature, a pair of firstalignment marks, a pair of second alignment marks, and a pair of thirdalignment marks. The first alignment marks are aligned along a firstdirection with the device feature and adjacent to opposite sides of thedevice feature. The second alignment marks are aligned along a seconddirection with the device feature that is substantially perpendicular tothe first direction, and adjacent to opposite sides of the devicefeature. The third alignment marks are aligned with the first alignmentmarks in the first direction and adjacent to opposite sides of thedevice feature, wherein the third marks are between the first alignmentmarks and the device feature, and each of the third marks have a shorterlength along the first direction than each of the first alignment marks.

According to further embodiments of the present invention, one of thesecond alignment marks may be on the device feature. The third alignmentmarks may be trenches in the semiconductor device. A pair of trench typefourth alignment marks may be directly connected to the first alignmentmarks and aligned therewith. The first alignment marks may be betweenthe fourth alignment marks and the device feature.

According to still further embodiments of the present invention, a firstauxiliary alignment mark may be aligned with the second alignment marksand the device feature along the second direction. One of the secondalignment marks may be between the first auxiliary alignment mark andthe device feature. The first auxiliary alignment mark may have avariable cross-section width along the first direction.

According to still further embodiments of the present invention, a sideface of the semiconductor device is ground in the second direction tosubstantially simultaneously expose the first alignment marks, thesecond alignment mark on the device feature, and the third alignmentmarks. An amount of the side face of the semiconductor device that is tobe removed by grinding to expose the first alignment marks, the secondalignment mark on the device feature, and the third alignment marks maybe estimated based on the cross-section width of the first auxiliaryalignment mark along the first direction. A rate of grinding of the sideface of the semiconductor device may be reduced based on thecross-section width of the first auxiliary alignment mark along thefirst direction. A rate of grinding of the side face of thesemiconductor device may be reduced based on exposure of a first one ofthe pair of second alignment marks. A rate of grinding of the side faceof the semiconductor device may be reduced based on exposure of thethird marks. The grinding of the side face of the semiconductor devicemay be stopped based on exposure of the second alignment mark on thedevice feature.

Some other embodiments of the present invention provide a method forexposing at least a portion of a defective device feature on asemiconductor device. A plurality of alignment marks are formed on thesemiconductor device. Portions of the semiconductor device are groundaway to expose the defective device feature. The rate of grinding isvaried based on the alignment marks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of alignment marks adjacent to a semiconductordevice feature in accordance with various embodiment of the presentinvention;

FIGS. 2 to 6 are cross sectional views that illustrate methods forforming alignment marks adjacent to a semiconductor device feature, andfor grinding the semiconductor device to expose a surface of the devicefeature in accordance with various embodiments of the present invention;and

FIGS. 7A to 7C are sequential plan views of a semiconductor device thathas been ground to expose a side surface of a device feature inaccordance with various embodiments of the present invention.

DETAILED DESCRIPTION

Certain embodiments of the present invention now will be described morefully hereinafter with reference to the accompanying drawings. Thisinvention may, however, be embodied in many different forms and shouldnot be construed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the invention to thoseskilled in the art.

In the drawings, the size and relative sizes of layers and regions maybe exaggerated for clarity. It will be understood that when an elementor layer is referred to as being “on”, “connected to” or “coupled to”another element or layer, it can be directly on, connected or coupled tothe other element or layer or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to” or “directly coupled to” another element orlayer, there are no intervening elements or layers present. Like numbersrefer to like elements throughout.

Embodiments of the present invention are described herein with referenceto cross-section illustrations that are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto, for example, the particular shapes of regions illustrated herein,but are to include deviations in shapes that result, for example, frommanufacturing. For example, an implanted, deposited, and/or etchedregion illustrated as a rectangle will, typically, have rounded orcurved features at its edges. Thus, the regions illustrated in thefigures are schematic in nature and their shapes are not intended toillustrate the precise shape of a region of a device and are notintended to limit the scope of the present invention.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Itwill be further understood that the terms “comprises” and/or“comprising,” when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a plan view of alignment marks that are adjacent to a devicefeature in accordance with various embodiments of the present invention.The device feature may be, for example, a failed memory cell or regiontherein. The alignment marks may be used to obtain a vertical profile ofthe device feature as will also be described later herein.

Referring to FIG. 1, a plan view is provided of a semiconductor device10 on which device features may be formed. One such device feature 12 isillustrated. The semiconductor device 10 may, for example, be a memorydevice in which the device feature 12 is a failed memory cell or region(e.g., a failed memory address). Alignment marks 20, 22, 24, 26, 28, and30 are formed on the semiconductor device 10 adjacent to the devicefeature 12, in accordance with various embodiments of the presentinvention. The alignment marks may be used to assist with locating thedevice feature 12 and obtaining a vertical profile thereof, such as bygrinding the semiconductor device 10, as will be described later herein.

For purposes of illustration only, the orientation and use of thealignment marks 20, 22, 24, 26, 28, and 30 will be described in thecontent of grinding a side face of the semiconductor device 10, which isparallel to the illustrated first direction, to remove materialtherefrom along the second direction and to expose a vertical profile ofthe device feature 12, in accordance with some embodiments of thepresent invention. The first direction is substantially perpendicular tothe second direction.

A first auxiliary alignment mark 20 is provided on the semiconductordevice 10 aligned with the device feature 12 along the second direction,and between the face that is to be ground and the device feature 12. Thefirst auxiliary alignment mark 20 may be used to determine the proximitybetween the side face of the semiconductor device 10 as it is grindedand the device feature 12. The first auxiliary alignment mark 20 may beformed as a trench in the semiconductor device 10. The first auxiliaryalignment mark 20 may also have a variable cross-section width along thefirst direction, such as a lozenge shape, a triangular shape, and/or acircular shape. Accordingly, the proximity to the side face of thesemiconductor device 10 and the device feature 12 may be determinedbased on an cross-section width of the first auxiliary alignment mark 20that is exposed by grinding. The rate of grinding of the side face ofthe semiconductor device 10 may then be controlled, and may be reduced,based on the cross-section width of the first auxiliary alignment mark20.

In certain embodiments of the present invention, the first auxiliaryalignment mark 20 may have a length of about 10 μm to about 100 μm inthe first and second directions, respectively. The first auxiliaryalignment mark 20 may be spaced apart from the device feature 12 toprovide a region on which other alignment marks may be formed.

A pair of first alignment marks 22 a and 22 b, referred to collectivelyas 22, are aligned with the device feature 12 along the first directionadjacent to opposite sides of the device feature 12. The first alignmentmarks 22 a and 22 b may include metal, and/or they may have a length ofabout 1 μm to about 5 μm in the first direction and a length of about0.5 μm to about 2 μm in the second direction.

A pair of second alignment marks 24 a and 24 b are aligned with thedevice feature 12 along the second direction, and are adjacent toopposite sides of the device feature 12. The second alignment marks 24 aand 24 b may include a metal such as platinum. The second alignment mark24 a is disposed between the device feature 12 and the first auxiliaryalignment mark 20 so that the proximity between the exposed side face ofthe semiconductor device 10 and the device feature 12 may be determinedbased on the second alignment mark 24 a. Accordingly, the rate ofgrinding of the side face of the semiconductor device 10 may then bereduced based on exposure of the second alignment mark 24 a.

The second alignment mark 24 b is disposed behind the device feature 12as viewed from the exposed side face of the semiconductor device 10, andmay contact and be on (e.g., overlap) the device feature 12. Thelocation of the device feature 12 along the first and second directionsmay thereby be determined based on the second alignment mark 24 b.During a grinding process, grinding of the side face of thesemiconductor device 10 may then be stopped based on exposure of thesecond alignment mark 24 b. When the second alignment mark 24 b becomesexposed, the side face of the semiconductor device 10 can include avertical profile of the device feature 12.

In certain embodiments of the present invention, each of the secondalignment marks 24 a and 24 b may have a length of about 0.1 μm to about1 μm in the first direction and a length of about 0.5 μm to about 2 μmin the second direction.

As shown in FIG. 1, a pair of third alignment marks 26 may be alignedwith the first alignment marks 22 a and 22 b in the first direction andadjacent to opposite sides of the device feature 12. The third alignmentmarks 26 may be between the first alignment marks 22 a and 22 b and thedevice-feature 12, and each of the third alignment marks 26 may have ashorter length along the first direction than each of the firstalignment marks 22 a and 22 b.

The third alignment marks 26 may comprise a trench in the semiconductordevice 10. The third alignment marks 26 may be used to determine thelocation of the device feature 12 in the second direction. The rate ofgrinding of the side face of the semiconductor device 10 may then bereduced based on exposure of the third alignment marks 26.

The third alignment marks 26 may have a length in the second directionof about 0.5 times to about 1.5 times a length of the device feature 12in the second direction. For example, the third marks 26 may have alength of about 0.5 μm to about 2 μm in the first direction and a lengthof about 50 nm to about 200 nm in the second direction.

A pair of fourth alignment marks 28 are on the semiconductor device 10and directly connected to the first alignment marks 22 a and 22 b andaligned therewith. The first alignment marks 22 a and 22 b are betweenthe fourth alignment marks and the device feature 12. The fourthalignment marks 28 may be used to determine whether the semiconductordevice 10 is ground horizontally, such as by whether the fourthalignment marks 28 and the first alignment marks 22 a and 22 b aresimultaneously exposed during a grinding process.

A pair of second auxiliary alignment marks 30 are formed as trenches inthe semiconductor device 10, and are offset from each other along thesecond direction, and are adjacent to opposite sides of the secondalignment mark 24 a. The second auxiliary alignment marks 30 may be usedto determine a proximity of the side face of the semiconductor device 10relative to the device feature 12 during a grinding process.

Further methods of forming the alignment marks are now discussed below.

The semiconductor device 10 with the device feature 12 may be initiallymodified so that the device feature 10 is nearly centered thereon. Thesemiconductor device 10, may, for example, have first and second lengthsof about 3 mm to about 10 mm in the first and second directions,respectively.

The semiconductor device 10 may be loaded into a focus ion beam (FIB)apparatus. Because the FIB apparatus can have a higher magnificationthan an optical microscope, the FIB apparatus may be used to count celladdresses based on recognition of surface features of the semiconductordevice 10. Additionally, the semiconductor device 10 may be partiallyetched and/or a layer may be partially formed on the semiconductordevice 10 using the FIB apparatus to form some of the alignment marks onthe semiconductor device 10.

The first alignment marks 22 a and 22 b may be formed by depositing ametal, such as platinum, aligned with the device feature 12 along thefirst direction, and on opposite sides of the device feature 12. Thefirst alignment marks 22 a and 22 b may have a length of about 1 μm toabout 5 μm in the first direction and a length of about 0.5 μm to about2 μm in the second direction. By forming the first alignment marks 22 aand 22 b by a deposition process, the first alignment marks 22 a and 22b can have a sufficient size so as to be optically observable, incontrast to such marks that may be formed by an etching process.Accordingly, a position of the device feature 12 in the second directionmay be determined by optical recognition of the first alignment marks 22a and 22 b.

The pair of second alignment marks 24 a and 24 b may be formed bydepositing a metal, such as platinum, on the semiconductor device 10,aligned with the device feature 12 along the second direction, andadjacent to opposite sides of the device feature 12. The secondalignment mark 24 b make be formed on a portion of the device feature12, and to overlap and/or contact the device feature. Accordingly, theposition of the device feature 12 in the first direction may bedetermined based on the second alignment mark 24 b. The second alignmentmarks 24 a and 24 b may have a length of about 0.1 μm to about 1 μm inthe first direction and a length of about 0.5 μm to about 2 μm in thesecond direction. Because the second alignment marks 24 a and 24 b maybe formed by a deposition process, they may be more readily observed byan optical process compared to if they were formed by an etchingprocess. Additionally, although the second alignment mark 24 b mayoverlap the device feature 12, the vertical profile of the devicefeature 12 may not be affected thereby.

The semiconductor device 10 may be partially etched in the firstdirection between the first alignment marks 22 a and 22 b and the devicefeature 12 to form the third alignment marks 26 as trenches. The etchingprocess may be carried out using a gallium ion in the FIB apparatus. Thedevice feature 12 may not be damaged by the etching process. The thirdalignment marks 26 can be used to determine a position of the devicefeature 12 in the second direction. A thickness of each of the thirdalignment marks 26 may be about 0.5 times to about 1.5 times that of thedevice feature 12 in the second direction. In particular, the thirdalignment marks 26 may have a length of about 0.5 μm to about 2 μm inthe first direction and the length of about 50 nm to about 200 nm in thesecond direction. The third alignment marks 26 may thereby be observableusing the optical microscope.

The semiconductor device 10 may be partially etched along outer ends ofthe first alignment marks 22 a and 22 b to form the fourth alignmentmarks 28 as trenches. The fourth alignment marks 28 may-thereby contactouter ends of the first alignment marks 22 a and 22 b. The fourthalignment marks 28 may be used to determine whether the semiconductordevice 10 is ground horizontally (i.e., in parallel). For example, thesemiconductor device 10 may be determined to be ground horizontally whenthe first alignment marks 22 a and 22 b and the fourth alignment marks28 are simultaneously exposed during the grinding process.

The semiconductor device 10 may also be partially etched to form thefirst auxiliary alignment mark 20. The first auxiliary alignment mark 20may be used to determine a proximity of the side face of thesemiconductor device 10 that is exposed during the grinding process andthe device feature 12. The cross-section width of the first auxiliaryalignment mark 20 varies based on distance from the exposed side face ofthe first auxiliary alignment mark 20 from the device feature 12. Thefirst auxiliary alignment mark 20 may, for example, have a lozengeshape, a triangular shape, and/or a circular shape.

The semiconductor device 10 may be partially etched to form the secondauxiliary alignment marks 30 as trenches. The second auxiliary alignmentmarks 30 can be offset relative to each other along the second directionand adjacent to opposite sides of the second alignment mark 24 a. Thesecond auxiliary alignment marks 30 may be used to determine theproximity of the side face of the semiconductor device 10 that isexposed during grinding to the device feature 12. For example, suchproximity may be determined based on the observed position of theexposed second auxiliary alignment marks 30 and the second alignmentmark 24 a. Accordingly, the rate of grinding of the side face of thesemiconductor device 10 may be reduced based on exposure of the secondalignment mark 24 a and/or based on exposure of one or both of thesecond auxiliary alignment marks 30.

As will be appreciated by one who is skilled in the art in light of thepresent disclosure, alignment marks may be oriented differently relativeto a device feature and may be formed by various other processesaccording to yet other embodiments

The alignment marks may thereby be used to assist with obtaining avertical profile of the device feature 12, and will now be discussed forpurposes of further illustration. The vertical profile may be used toanalyze, for example, an abnormality in a process for doping impuritiesinto source/drain regions, or other regions in the semiconductor device10. The vertical profile may allow analysis that would not otherwise bepossible through examination of the surface of a semiconductor device.To obtain a vertical profile of the device feature 12, a side face ofthe semiconductor device 10 is ground to expose the device feature 12.

FIGS. 2 to 6 are cross sectional views that illustrate methods forfabricating a device that is used for analyzing the vertical profile ofa device feature in accordance with various embodiment of the presentinvention. FIGS. 7A to 7C are plan views illustrating a device that issubsequently ground.

Referring to FIG. 2, a glass layer 102 is deposited or attached on anupper face of the semiconductor device 10. The glass layer 102 mayprotect the semiconductor device 10 during a subsequent grindingprocess. At least one dummy substrate 100 may be attached on a lowerface of the semiconductor device 10. The dummy substrate 100 may be usedto adjust the thickness of the semiconductor device 10 during thegrinding process.

Referring to FIGS. 3A and 3B, a side face of the semiconductor device 10is first ground in the second direction (see FIG. 1) to remove the firstauxiliary alignment mark 20. In particular, the side face of thesemiconductor device 10 may be continuously observed with an opticalmicroscope during the grinding process. When the first auxiliaryalignment mark 20 has a lozenge shape, the first auxiliary alignmentmark 20 observed with the optical microscope in an initial stage of theprimary grinding process has a very small cross-section width. When thefirst grinding process advances to a middle stage, as shown in FIG. 3A,the first auxiliary alignment mark 20 observed with the opticalmicroscope has relatively larger cross-section width. When the firstgrinding process advances to a final stage, as shown in FIG. 3B, thefirst auxiliary alignment mark 20 observed with the optical microscopehas a relatively small cross-section width, and may eventually not beobserved through the optical microscope. FIG. 7A is a plan viewillustrating the first ground semiconductor device 10.

Referring to FIGS. 4A and 4B, the semiconductor device 10 may then besecond ground in the second direction to remove the second alignmentmark 24 a. During the grinding process, the second alignment mark 24 ais exposed through the side face of the semiconductor device 10. Asshown in FIG. 4B, the illustrated right second auxiliary alignment mark30 is also simultaneously exposed. As the second grinding processadvances, the right second auxiliary alignment mark 30 disappears and,subsequently, the left second auxiliary alignment mark 30 becomesexposed, as shown in FIG. 4A.

Here, as described above, the second auxiliary alignment marks 30 areoffset relative to each other along the second direction. Accordingly,the proximity between the exposed side face of the semiconductor device10 and the device feature 12 may be determined based on exposure of theright and then left second auxiliary alignment marks 30. When the leftsecond auxiliary alignment mark 30 is exposed, it is noted that theexposed side face of the semiconductor device 10 has closely approachedthe device feature 12. Accordingly, a rate at which the side face of thesemiconductor device 10 is ground toward the device feature 12 may bereduced. FIG. 7B is a plan view illustrating the semiconductor device 10after the second grinding process is completed.

Referring to FIG. 5, the semiconductor device 10 is subject to a thirdgrinding process to expose the first and fourth alignment marks 22 and28. Because the third grinding process is performed at a stage where theexposed side face of the semiconductor device 10 is nearly adjacent tothe device feature 12, the grinding process may have a very slow speed.Also, the exposed side face of the semiconductor device 10 may befrequently observed to prevent the device feature 12 from being ground.The grinding of the exposed side face of the semiconductor device 10 maybe controlled so as to be horizontally ground by observing with theoptical microscope that the first and fourth alignment marks 22 and 28are parallel.

When the third grinding process is completed, the semiconductor device10 has a side face that exposes the device feature 12. This verticalprofile of the device feature 12 may then be further analyzed. Forexample, the vertical profile may be analyzed to determine a dopingprofile of the impurities in the device feature 12, and/or a dopingdepth, such as of a gate in a transistor, may be analyzed in the devicefeature 12.

The second alignment mark 24 b that is behind the device feature 12 isexposed through the side face of the semiconductor device 10 when thedevice feature 12 is exposed. The first alignment marks 22 a and 22 b,the third alignment marks 26 and the fourth alignment marks 28 are alsoexposed through the side face of the semiconductor device 10.Accordingly, the position of the device feature 12 on the side face ofthe semiconductor device 10 may be precisely determined using the secondalignment mark 24 b and the third alignment marks 26. FIG. 7C is a planview illustrating the semiconductor device 10 after completion of thethird grinding process.

FIG. 6 is a cross sectional view that illustrates the semiconductordevice 10 if the device feature 12 is removed. The device feature 12 maybe removed by excessive grinding of the semiconductor device 10.However, by use of the alignment marks described herein, such excessivegrinding may be avoided.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

1. A method for forming alignment marks on a semiconductor device havinga device feature, the method comprising: forming a pair of firstalignment marks on the semiconductor device that are aligned along afirst direction with the device feature and adjacent to opposite sidesof the device feature; forming a pair of second alignment marks on thesemiconductor device that are aligned along a second direction with thedevice feature, which is substantially perpendicular to the firstdirection, and adjacent to opposite sides of the device feature; andforming a pair of third alignment marks on the semiconductor device thatare aligned with the first alignment marks in the first direction andadjacent to opposite sides of the device feature, wherein the thirdalignment marks are between the first alignment marks and the devicefeature, and each of the third alignment marks have a shorter lengthalong the first direction than each of the first alignment marks.
 2. Themethod of claim 1, wherein: forming a pair of first alignment markscomprises depositing the first alignment marks on the semiconductordevice; and forming a pair of second alignment marks comprisesdepositing the second alignment marks on the semiconductor device. 3.The method of claim 1, wherein forming a pair of second alignment markscomprises forming one of the second alignment marks on the devicefeature.
 4. The method of claim 1, wherein forming a pair of thirdalignment marks comprises etching the semiconductor device to generate apair of trenches that are aligned with the first alignment marks in thefirst direction and adjacent to opposite sides of the device feature,wherein the pair of trenches are between the first alignment marks andthe device feature, and each of the trenches have a shorter length alongthe first direction than each of the first alignment marks.
 5. Themethod of claim 1, further comprising etching the semiconductor deviceto form a pair of trenches as fourth alignment marks directly connectedto the first alignment marks and aligned therewith, wherein the firstalignment marks are between the fourth alignment marks and the devicefeature.
 6. The method of claim 1, further comprising forming a firstauxiliary alignment mark on the semiconductor device that is alignedwith the second alignment marks and the device feature along the seconddirection, wherein one of the second alignment marks is between thefirst auxiliary alignment mark and the device feature, and wherein thefirst auxiliary alignment mark has a variable cross-section width alongthe first direction.
 7. The method of claim 6, wherein the firstauxiliary alignment mark has at least one of a lozenge shape, atriangular shape, and a circular shape.
 8. The method of claim 1,further comprising etching the semiconductor device to form a pair oftrenches as second auxiliary alignment marks that are offset along thesecond direction from each other, and are adjacent to opposite sides ofone of the second alignment marks.
 9. The method of claim 1, whereineach of the third alignment marks have a length in the second directionthat is about 0.5 times to about 1.5 times a length of the devicefeature in the second direction.
 10. The method of claim 1, wherein eachof the third alignment marks have a length in the first direction ofabout 0.5 μm to about 2 μm and a length in the second direction of about0.05 μm to about 0.2 μm.
 11. The method of claim 10, wherein each of thefirst alignment marks have a length in the first direction of about 1 μmto about 5 μm and a length in the second direction of about 0.5 μm toabout 2 μm.
 12. The method of claim 11, wherein each of the secondalignment marks have a length in the first direction of about 0.1 μm toabout 1 μm and a length in the second direction of about 0.5 μm to about2 μm.